The present invention generally relates to a nonvolatile semiconductor memory device and a manufacturing method thereof. More particularly, the present invention relates to a memory-element array method of a semiconductor memory device which uses a non-conductive charge trapping layer for memory elements.
MONOS (Metal Oxide Nitride Oxide Silicon) memory technology has been proposed in response to recent improvement in integration and reduction in costs of nonvolatile semiconductor memory devices. The MONOS memory technology is characterized in that a non-conductive charge trapping layer (e.g., SiN) is used for memory elements and charges are locally trapped in the charge trapping layer.
Conventional MONOS memories can store only one-bit data in each memory cell because charges are accumulated in the whole non-conductive charge trapping layer in gate regions. In recently developed local-trapping MONOS memory technology, however, charges are locally trapped in a non-conductive charge trapping layer (e.g., SiN), which enables 2-bit data to be stored in each memory cell. The local-trapping MONOS memory technology is therefore advantageous for improvement in integration and reduction in costs.
However, local-trapping MONOS memories can malfunction when charges are accumulated in a non-conductive charge trapping layer due to ultraviolet (UV) rays which are generated during the manufacturing process.
A technology of forming a UV absorbing layer under first metal wirings has been proposed in view of the above problem (e.g., Japanese Laid-Open Patent Publication No. 2003-243545).
Hereinafter, a conventional example in which a UV absorbing layer is formed under first metal wirings will be described with reference to the figures.
First, a memory cell array structure will be described with reference to the figures.
FIG. 25 is a circuit diagram showing an electric connection method of a common memory cell array.
As shown in FIG. 25, word lines (WL0a, WL1a, WL2a, WL3a) extend in the row direction (word-line direction) and bit lines (BL0a, BL1a, BL2a, BL3a, BL4a) extend in the column direction (bit-line direction). Although not shown in FIG. 25, a memory cell array is usually formed from a multiplicity of word lines and a multiplicity of bit lines. For simplicity, FIG. 25 shows a circuit diagram of only sixteen memory cells. Word lines electrically connect gate electrodes of memory cells arranged in the row direction, and bit lines electrically connect source/drain diffusion layers of memory cells arranged in the column direction. Source/drain diffusion layers of adjacent memory cells in the row direction are electrically short-circuited. Memory cells can thus be densely arranged in a memory cell array.
FIG. 26 is a plan view of the memory cell array shown in FIG. 25.
As shown in FIG. 26, word line electrodes 2 extend in the row direction and bit line diffusion layers 1 extend in the column direction. Each word line electrode 2 forms a word line (WL0a, WL1a, WL2a, WL3a) and each bit line diffusion layer 1 forms a bit line (BL0a, BL1a, BL2a, BL3a, BL4a). An isolation diffusion layer 3 is formed between adjacent bit line diffusion layers 1 in order to electrically isolate adjacent bit line diffusion layers 1 from each other. A contact 4 is formed every few bits for each bit line diffusion layer 1 and each word line electrode 2. Each bit line diffusion layer 1 and each word line electrode 2 are electrically connected to a corresponding metal wiring (not shown) through corresponding contacts 4. A UV absorbing layer 5 covers the memory cell array. Functions of the UV absorbing layer 5 will be described later.
FIG. 27 is a plan view of the memory cell array and shows cutting planes A-A, B-B, C-C and D-D corresponding to the cross-sectional views of FIG. 28 through FIG. 36A and 36B.
FIG. 28 is a cross-sectional view of the memory cell array taken along line A-A of FIG. 27.
As shown in FIG. 28, the memory cell array includes a P-type well 11, bit line diffusion layers 1, a non-conductive charge trapping layer 12, word line electrodes 2, a first interlayer insulating film 13, a UV absorbing layer 5, a first additional interlayer insulating film 14, contacts 4, first metal wirings 15, a second interlayer insulating film 16, first via holes 17, second metal wirings 18, and a surface protective film 19. Each second metal wiring 18 is electrically connected to a corresponding word line electrode 2 every few bits through corresponding first via holes 17, two of the six first metal wirings 15 shown in the figure (i.e., the ones located at both ends), and corresponding contacts 4 in order to reduce the word line resistance. Each of the remaining four first metal wirings 15 (the middle four first metal wirings) is electrically connected to a corresponding bit line diffusion layer 1 every few bits (see FIG. 30) in order to reduce the bit line resistance.
FIG. 29 is a cross-sectional view of the memory cell array taken along line B-B in FIG. 27.
As shown in FIG. 29, bit line diffusion layers 1 and isolation diffusion layers 3 are alternately formed between the charge trapping layer 12 and the P-type well 11. Adjacent bit line diffusion layers 1 are thus electrically isolated from each other by the isolation diffusion layers 3 and the P-type well 11.
FIG. 30 is a cross-sectional view of the memory cell array taken along line C-C of FIG. 27.
As shown in FIG. 30, each first metal wiring 15 is electrically connected to a corresponding bit line diffusion layer 1 every few bits through corresponding contacts 4 in order to reduce the bit line resistance. As described above, each second metal wiring 18 is electrically connected to a corresponding word line electrode 2 every few bits (see FIG. 31) in order to reduce the word line resistance.
FIG. 31 is a cross-sectional view of the memory cell array taken along line D-D of FIG. 27.
As shown in FIG. 31, the isolation diffusion layers 3 are formed in the P-type well 11 in a self-aligned manner so that adjacent word line electrodes 2 are electrically isolated from each other.
FIG. 32A is a cross-sectional view (in the gate length direction) of a single memory cell which is formed from the P-type well 11, bit line diffusion layers 1, the charge trapping layer 12 and a word line electrode 2 in FIG. 28.
As shown in FIG. 32A, a bit line diffusion layer 1a serves as a drain portion, a bit line diffusion layer 1b serves as a source portion, the P-type well 11 serves as a channel portion, the charge trapping layer 12 (non-conductive) serves as a gate insulating film, and the word line electrode 2 serves as a gate electrode. The memory transistor of FIG. 32A therefore has the same functions as those of a common MOS (Metal Oxide Semiconductor) transistor. The memory transistor of FIG. 32A is different from a common MOS transistor in that the drain portion (bit line diffusion layer 1a) and the source portion (bit line diffusion layer 1b) are embedded under the gate electrode (word line electrode 2) and in that the gate insulating film is formed from the charge trapping layer 12. Note that the bit line diffusion layers 1a and 1b are herein respectively referred to as a drain portion and a source portion based on their functions in read operation (see FIG. 33C).
FIG. 32B is a cross-sectional view (in the gate width direction) of a single memory cell which is formed from the P-type well 11, the isolation diffusion layers 3, the charge trapping layer 12 and a word line electrode 2 in FIG. 31.
As shown in FIG. 32B, the width of the P-type well 11 interposed between the isolation diffusion layers 3 is a gate width.
Basic operation of the memory cell shown in FIGS. 32A and 32B will be described with reference to FIGS. 33A to 33C.
FIG. 33A illustrates write operation of the memory cell. Like FIG. 32A, FIG. 33A is a cross-sectional view of the memory cell in the gate length direction.
As shown in FIG. 33A, a voltage of 10V is applied to the word line electrode 2, 5V is applied to the bit line diffusion layer 1b, 0V is applied to the bit line diffusion layer 1a and 0V is applied to the P-type well 11. As a result, channel hot electrons are generated in the boundary region between the bit line diffusion layer 1b and the P-type well 11. Electrons thus generated are injected into the charge trapping layer 12. More specifically, electrons are locally injected into a region of the charge trapping layer 12 which is located on the boundary region between the bit line diffusion layer 1b and the P-type well 11.
FIG. 33B illustrates erase operation of the memory cell. Like FIG. 32A, FIG. 33B is a cross-sectional view of the memory cell in the gate length direction.
As shown in FIG. 33B, a voltage of −6V is applied to the word line electrode 2, 5V is applied to the bit line diffusion layer 1b, 0V is applied to the bit line diffusion layer 1a and 0V is applied to the P-type well 11. As a result, hot holes are generated in the boundary region between the bit line diffusion layer 1b and the P-type well 11 due to an interband tunneling current. Holes thus generated are injected into the charge trapping layer 12. Electrons injected in the write operation are thus electrically neutralized.
FIG. 33C illustrates read operation of the memory cell. Like FIG. 32A, FIG. 33C is a cross-sectional view of the memory cell in the gate length direction.
As shown in FIG. 33C, a voltage of 4V is applied to the word line electrode 2, 0V is applied to the bit line diffusion layer 1b, 1V is applied to the bit line diffusion layer 1a, and 0V is applied to the P-type well 11. When data has been stored in the memory cell, electrons have been trapped in the region of the charge trapping layer 12 which is close to the bit line diffusion layer 1b. The memory cell therefore has a high threshold voltage, and a source-drain current does not flow in response to the voltage application. On the other hand, when data has been erased from the memory cell, electrons trapped in write operation have been electrically neutralized in the region of the charge trapping layer 12 which is close to the bit line diffusion layer 1b. The memory cell therefore has a low threshold voltage, and a source-drain current flows in response to the voltage application.
Local-trapping MONOS memories are thus characterized in that electrons are locally trapped in the charge trapping layer 12 and in that a source-drain current flows in the opposite directions in write operation and read operation.
Hereinafter, the effects of the UV absorbing layer 5 will be described with reference to FIG. 34 to FIGS. 36A and 36B.
In a semiconductor manufacturing process, ultraviolet (UV) rays (λ<400 nm) are generated in various processes such as a lithography process, a plasma CVD (Chemical Vapor Deposition) process and a reactive ion etching process. In particular, UV rays having energy exceeding 4.3 eV (λ<290 nm) excite electrons in the substrate and accumulate electrons in the charge trapping layer 12.
Hereinafter, effects of UV rays which are generated after formation of the first metal wirings 15 will be described by way of example.
FIG. 34 is a cross-sectional view of the memory cell array taken along line B-B of FIG. 27. It is assumed in FIG. 34 that the memory cell array does not have the UV absorbing layer 5.
As shown in FIG. 34, the first metal wirings 15 reflect UV rays and function as a light-shielding film. As can be seen from FIG. 34, however, UV rays reach the isolation diffusion layers 3 through the regions between the first metal wirings 15. Therefore, charges are accumulated in the regions of the charge trapping layer 12 which are located on the isolation diffusion layers 3.
Like FIG. 32B, FIG. 35 is a cross-sectional view of a single memory cell in the memory cell array taken along line D-D of FIG. 27. In FIG. 35, UV rays generated during the manufacturing process have caused electrons to be accumulated in the regions of the charge trapping layer 12 which are located on the isolation diffusion layers 3.
As can be seen from FIG. 35, electrons have been trapped not only in the regions of the charge trapping layer 12 which are not covered by the first metal wirings 5 but also in the regions of the charge trapping layer 12 which are located under both ends of the word line electrode 2 which face the isolation diffusion layers 3. This is caused primarily by UV rays which are reflected in an oblique direction.
Like FIG. 32A, FIG. 36A is a cross-sectional view of a single memory cell in the memory cell array taken along line A-A of FIG. 27. FIG. 36A shows the same state as that of FIG. 35. In FIG. 36A, line A-A runs through the central region of the word line electrode 2.
As can be seen from FIG. 36A, electrons have not been trapped in the central region of the word line electrode 2. As described above with respect to FIG. 35, electrons are trapped not only in the regions of the charge trapping layer 12 which are not covered by the first metal wirings 5 but also in the regions of the charge trapping layer 12 which are located under both ends of the word line electrode 2 which face the isolation diffusion layers 3. As shown in FIG. 35, however, electrons are not trapped in the region of the charge trapping layer 12 which is located under the central region of the word line electrode 2. Therefore, electrons have not been trapped in the charge trapping layer 12 in FIG. 36A.
Like FIG. 32A, FIG. 36B is a cross-sectional view of a single memory cell in the memory cell array taken along line A-A of FIG. 27. FIG. 36B shows the same state as that of FIG. 35. In FIG. 36B, line A-A runs through an end (edge region) of the word line electrode 2.
As can be seen from FIG. 36B, electrons have been trapped in the region of the charge trapping layer 12 which is located under the end of the word line electrode 2. As described above with respect to FIG. 35, electrons are trapped not only in the regions of the charge trapping layer 12 which are not covered by the first metal wirings 15 but also in the regions of the charge trapping layer 12 which are located under both ends of the word line electrode 2 which face the isolation diffusion layers 3. Therefore, electrons have been trapped in the charge trapping layer 12 in FIG. 36B.
As shown in FIG. 36B, under the end of the word line electrode 2, electrons have been trapped in the entire charge trapping layer 12 in the gate length direction. In this case, a threshold voltage is increased in this region. When a threshold voltage is increased in a large region of the charge trapping layer 12 in the gate width direction as shown in FIG. 35, erase operation of memory cells cannot be conducted as described with respect to FIG. 33B, impairing memory operation.
In view of the above problems, the conventional example has the UV absorbing layer 5 under the first metal wirings 15 as shown in FIGS. 26 to 31 in order to prevent increase in threshold voltage of memory cells due to UV rays which are generated during the manufacturing process.
However, when dimensions of wirings of bit line diffusion layers are reduced for miniaturization of nonvolatile semiconductor memory devices, the bit line resistance is increased, thereby impairing memory operation.
Bit lines can be formed from metal wirings in order to reduce the bit line resistance, but this causes the following problems.
The above conventional example has the UV absorbing layer 5 between the first interlayer insulating film 13 and the first additional interlayer insulating film 14 in order to suppress increase in threshold voltage of memory cells. This structure can be used because the contacts 4 are formed in the peripheral region of the memory cell array.
When bit lines are formed from metal wirings, it is usually required to form the contacts 4 all over the memory cell array. Therefore, when bit lines are formed from metal wirings, the use of the structure of the conventional example is not practical for the following reasons: holes for the contacts 4 need to be formed in the UV absorbing layer 5; and the UV absorbing layer 5 must be formed from a material that is capable of suppressing a leakage current to approximately zero (about 0.1 μA or less between bit lines) in order to suppress a leakage current through the UV absorbing layer 5. It is therefore extremely important how to eliminate the effects of UV rays which are generated during the manufacturing process.